1. Field of the Invention
This invention relates to a solid-state image sensing apparatus and particularly to a solid-state image sensing apparatus which can sum pixel signals.
2. Description of the Related Art
In recent years, in a field of a mobile terminal such as a cellular phone, one with a function to photograph has been widespread. As for the function to photograph which a mobile terminal has, high pixel density (mega pixels) for higher picture quality of a still picture is required and a mobile terminal with the function to photograph is expected to replace a low-cost Digital Still Camera (DSC). On the other hand, the function to photograph which a mobile terminal has is required to be compliant with a picture less than QVGA (about 80,000 pixels), considering animations and communication.
To meet these requirements, in a CCD solid-state image sensing apparatus with high pixel density, so-called mega pixels, for example, removal of pixels by partial sampling of pictures called cull is executed. Additionally, a sum of pixel signals in a vertical direction is performed in an amplifying-type solid-state image sensing apparatus.
FIG. 1 is a diagram showing a circuit structure of “Solid-state image sensing apparatus” (refer to Japanese Laid-Open Patent application No. 2000-106653) and an example of a solid-state image sensing apparatus in which a sum of pixel signals in a vertical direction is performed.
A conventional solid-state image sensing apparatus includes: a unit cell 500 which is composed of a photodiode 501 which converts light to charge, a readout transistor 502 which reads out the signal of the photodiode 501, an amplifier transistor 503 which amplifies the signal voltage of the photodiode 501, a reset transistor 504 which resets the signal voltage of the photodiode 501, a vertical selection transistor 505 which selects the row from which the amplified signal voltage is read out, a Floating Diffusion (FD) unit 506 which detects the signal voltage of the photodiode 501; an image area 510 where n×m pieces of the unit cells 500 are laid out two-dimensionally; the first vertical signal line 520 which transmits the signal voltage of the unit cell 500 to a signal process unit 550 column-by-column; a row selection circuit 530 which selects the unit cell 500 row-by-row; a group of load transistors 540; the signal process unit 550 which retains the signal voltage transmitted through the vertical signal line 520 and cuts noise; a column selection circuit 560 which selects the unit cell 500 column-by-column; a horizontal signal line 570 which transmits the signal voltage outputted from the signal process unit 550 to an output amplifier 580; and the output amplifier 580. In FIG. 5, to simplify an explanation, the unit cell 500 in the “n”th row and the “m”th column is shown.
FIG. 2 is a diagram showing a circuit structure of the signal process unit 550.
The signal process unit 550 includes: a sample hold transistor 600 connected to the first vertical signal line 520; a clamp capacitor 610 connected to the first vertical signal line 520 through the sample hold transistor 600; the second vertical signal line 620 connected to the first signal vertical line 610 through the clamp capacitor 610; sampling transistors 630a, 630b and 630c connected to the second vertical signal line 620; a clamp transistor 640; a column selection transistor 650 connected to the second vertical signal line 620; sampling capacitor 660a connected to the second vertical signal line 620 through the sampling transistor 630a; sampling capacitor 660b connected to the second vertical signal line 620 through the sampling transistor 630b; and sampling capacitor 660c connected to the second vertical signal line 620 through the sampling transistor 630c. 
Corresponding to an application of a sampling pulse which makes an SP line high level, the sample holding transistor 600 becomes ON state and transmits the signal voltage transmitted from the first vertical signal line 520 to the clamp capacitor 610.
Additionally, corresponding to an application of a clamp pulse which makes a CP line high level, the clamp transistor 640 becomes ON state, CPDC voltage is provided to a terminal B of the clamp capacitor 610. By maintaining the voltage between the terminals A and B at the time of a reset, the clamp capacitor 610 removes fixed pattern noises different for each unit cell 500. Here, capacitance of the clamp capacitor is Ccp.
The second vertical signal line 620 transmits the signal voltage transmitted from the first vertical signal line 520 through the clamp capacitor 610.
Corresponding to an application of a capacitor selection pulse A which makes an SWA line high level, the sample holding transistor 630a becomes ON state and transfers the signal voltage transmitted through the second vertical signal line 620 to the sampling capacitor 660a. Additionally, corresponding to an application of a capacitor selection pulse B which makes an SWB line high level, the sample holding transistor 630b becomes ON state and transfers the signal voltage transmitted through the second vertical signal line 620 to the sampling capacitor 660b. Then, corresponding to an application of a capacitor selection pulse C which makes an SWC line high level, the sample holding transistor 630c becomes ON state and transfers the signal voltage transmitted through the second vertical signal line 620 to the sampling capacitor 660c. 
Corresponding to an application of the clamp pulse which makes the CP line high level, the clamp transistor 640 becomes ON state and resets, to the electric potential of the CPDC line, the second vertial signal line 620, the clamp capacitor 610, the sampling capacitors, 660a, 660b and 660c. 
Corresponding to an application of a column selection pulse which makes a CSEL line high level, the column selection transistor 650 becomes ON state and transfers charges accumulated in sampling capacitors 660a, 660b and 660c to the horizontal signal line 570.
Each of the sampling capacitors 660a, 660b and 660c accumulates signal voltage readout for each row. For example, the sampling capacitor 600a accumulates the signal voltage read out from the unit cell 500 in the “n”th row; the sampling capacitor 600b accumulates the signal voltage read out from the unit cell 500 in the “(n−1)”th row; and the sampling capacitor 600c accumulates the signal voltage read out from the unit cell 500 in the “(n−2)”th row. Here, the capacitance of the capacitor 660a is Csp; the capacitance of the capacitor 660b is Csp; and the capacitance of the capacitor 660c is Csp.
Operations of the conventional solid-state image sensing apparatus described above are explained based on a drive timing chart shown in FIG. 3.
When the unit cell 500 in the “n”th row is selected, a row selection pulse (n) which makes a LSET (n) line high level is applied to a vertical selection transistor 505 of the unit cell 500 in the “n”th row. As a result, the vertical selection transistor 505 becomes ON state; the amplifier transistor 503 and the group of load transistors 540 form a source follower circuit; and voltage which follows power supply voltage of the unit cell 500 is outputted from the source follower circuit to the first vertical signal line 520.
Next, the sampling pulse which makes the SP line high level is applied to the sample hold transistor 600. As a result, the sample hold transistor 600 becomes ON state and holds the voltage outputted from the source follower circuit to the first vertical signal line 520 in the clamp capacitor 610. At this time, the clamp pulse which makes the CP line high level is applied to the clamp transistor 640. As a result, the clamp transistor becomes ON state; the clamp capacitor 610 at the side connected to the second vertical signal line 620 is reset to electric potential of the CPDC line. Additionally, since a capacitor selection pulse A which makes the SWA line high level is applied at the same time, the sampling transistor 630a becomes ON state and the sampling capacitor 660a is reset to electric potential of the CPDC line.
Next, a reset pulse (n) which makes a RESET (n) line high level is applied to the reset transistor 504. As a result, the reset transistor 504 becomes ON state and electric potential of the FD unit 506 is reset. The gate voltage of the amplifier transistor 503 connected to the FD unit 506 becomes the electric potential of the FD unit 506 and the voltage corresponding to this voltage, concretely the voltage given by (the electric potential of the FD unit−Vt)×a is outputted to the first vertical signal line 520. Here, Vt is threshold voltage of the amplifier transistor 503; a is a voltage amplification factor.
Next, the clamp pulse which makes the CP line low level is applied to the clamp transistor 640. As a result, the clamp transistor 640 becomes OFF state and the second vertical signal line 620 becomes floating state.
Next, a readout pulse (n) which makes a READ (n) line high level is applied to the readout transistor 502. As a result, the readout transistor 502 becomes ON state and signal charge accumulated in the photodiode 501 is transferred to the FD unit 506. The gate voltage of the amplifier transistor 503 connected to the FD unit 506 becomes the electric potential of the FD unit 506 and the voltage corresponding to this voltage, concretely the voltage given by (the electric potential of the FD unit−Vt)×a is outputted to the first vertical signal line 520. At this time, since the clamp pulse which makes the CP line low level is applied to the clamp transistor 640, the clamp transistor becomes OFF state, and in the sampling capacitor 660a is accumulated, as the signal voltage of the unit cell 500 in the “n”th row, voltage change corresponding to the difference between the voltage outputted to the first vertical signal line 520 when the electric potential of the FD unit 506 is reset and the voltage outputted to the first vertical signal line 520 when the signal charge accumulated in the photodiode 501 is transferred to the FD unit 506. Then, the capacitor selection pulse A which makes the SWA line low level is applied and the sampling transistor 630 becomes OFF state.
Next, the unit cell 500 in the “(n−1)”th row is selected; the capacitor selection pulse B which makes the SWB line high level is applied; similar operations are repeated; and in the sampling capacitor 660b is accumulated the signal voltage of the unit cell 500 in the “(n−1)”th row. Then, the capacitor selection pulse B which makes the SWB line low level is applied and the sampling transistor 630b becomes OFF state.
Next, the unit cell 500 in the “(n−2)”th row is selected; the capacitor selection pulse C which makes the SWC line high level is applied; similar operations are repeated; and in the sampling capacitor 660c is accumulated the signal voltage of the unit cell 500 in the “(n−2)” row. Then, the capacitor selection pulse C which makes the SWC line low level is applied and the sampling transistor 630c becomes OFF state.
Next, the capacitor selection pulse A, the capacitor selection pulse B and the capacitor selection pulse C are applied at the same time to make the SWA line, and the SWB line and SWC line high level, respectively. As a result, sampling transistors 630a, 630b and 630c become ON state.
Next, the column selection pulse (m) which makes the CSEL (m) line high level, the column selection pulse (m−1) which makes the CSEL (m−1) line high level and so on are applied to the column selection transistor 650 in sequence. As a result, each column selection transistor 650 becomes ON state in sequence, signal voltage accumulated in the sampling capacitor 660a, the sampling capacitor 660b and the sampling capacitor 660c are summed and outputted to the horizontal signal line 570 in sequence.
In the operations described above, in order to accumulate the signal voltage of the unit cell 500 in the “n”th row in the sampling capacitor 660a, the clamp transistor 640 and the column selection transistor 650 become OFF state and the sampling transistor 630a becomes ON state. As a result, the gain of a circuit formed by the clamp capacitor 610 and the sampling capacitor 660a is calculated and expressed by the equation (1).G=Ccp/(Ccp+Csp)  (1)
Here, in order to accumulate the signal voltage of the unit cells 500 in the “(n−1)” th row and the “(n−2)” th row in the sampling capacitors 660b and 660c, the gain of a circuit formed by the clamp capacitor 610 and the sampling capacitor 660b and the gain of a circuit formed by the clamp capacitor 610 and the sampling capacitor 660c are similarly calculated by the equation (1).
By the way, in a conventional solid-sate image sensing apparatus, capacitance per unit area of the clamp capacitor 610, the sampling capacitors 660a, 660b and 660c are some fF/μm2. Therefore, in the case of forming a capacitor of some pF, the area of the signal processing unit 550 is enlarged and the circuit formed to sum pixel signals enlarges the chip area. For example, when Ccp and Csp are 5 pF and the capacitance per unit area of the sampling capacitors 660a, 660b and 660c is 5 fF/μm2, the each area of the clamp capacitor 610, the sampling capacitors 660a, 660b and 660c is 1,000 μm2, which means the total is a large area of 4,000 μm2. Consequently, the capacitor length is 1,000 μm when the capacitor width in the horizontal direction of the clamp capacitor and the sampling capacitor is formed by 4 μm.
However, when a conventional solid-state image sensing apparatus does not sum the signal voltage, but accumulates the signal voltage using any of the sampling capacitors 660a, 660b and 660c and outputs the accumulated signal voltage to the horizontal signal line 570, the smaller the sampling capacitance Csp is, the more susceptible is the outputted signal voltage to an external noise caused by ON/OFF of the column selection transistor 650. Therefore, to restrain the influence of the external noise, it is unavoidable that the sampling capacitance Csp becomes large and there is a problem that the chip area enlarges. For example, when the gate capacitor of the column selection transistor has 4 fF (it is supposed that the gate size is about W/L=5 μm/1 μm and half of the gate capacitor has influenced as the external noise to the sampling capacitor) and pulse voltage of 3V is applied to the column selection transistor, voltage of 3V×4 f/(4 f+Csp) will jump into the signal voltage accumulated in the sampling capacitor in calculation. Consequently, if the signal voltage of 500 mV is accumulated in the sampling capacitor as a saturating signal, to make an S/N ratio of the external noise to the signal voltage—40 dB or less, when the sampling capacitor is the sampling capacitor>>the gate capacitor and the pulse voltage is VIN, it is necessary to satisfy the following equation: the saturating signal voltage/100>VIN×the gate capacitor/the sampling capacitor. Therefore, large capacitance of sampling capacitor of about 2.4 pF or more, about 600 times as large as capacitance of the gate capacitor affected by the external noise, is necessary. Additionally, when about 10% of the above-mentioned external noise is generated among the column selection transistors as unevenness of the external noise, large sampling capacitor, same value of about 2.4 pF or more, is necessary to make the S/N ratio at the time −60 dB or less.
Additionally, when the signals are not summed in the conventional solid-state image sensing apparatus, if a method of using simply a plurality of sampling capacitors is employed, a problem that circuit gain significantly reduces occurs. In other words, when the signals are not summed, and the signals are accumulated using, for example, 3 sampling capacitors, the sensibility of reading out the signals to the horizontal signal line 570 through the column selection transistor 650 is 3 Csp/(3 Csp+Ccom) if the capacitance of a common signaling line is Ccom. It is improvement compared with Csp/(Csp+Ccom), the circuit gain at this part when one sampling capacitor is used. However, the gain based on the equation (1) is, on the contrary, Ccp/(Ccp+3 Csp); the circuit gain reduces compared with Ccp/(Ccp+Csp) when one sampling capacitor is used; and transmission efficiency deteriorates. At this time, it is possible to restrain the reduction of the circuit gain calculated by the equation (1) by enlarging Ccp, the capacitance of the clamp capacitor for capacitance of the sampling capacitor. However, since Ccp, the capacitance of the clamp capacitor at the time, becomes a large value of several pF to several tens of pF, the problem that the chip area enlarges occurs. For example, to equalize the gain, in the case of increasing capacitance of the clamp capacitor by 10 pF because the sampling capacitor to be used has increased, it is necessary to increase the capacitor length by further 500 μm. Additionally, it is possible to make the circuit gain when signals of three sampling capacitors are read out at the same time three times larger by making Csp>>Ccom and Ccp>>Csp than the circuit gain in the case of not making Csp>>Ccom and Ccp>>Csp. However, since the capacitance of the horizontal common signal line is several pF˜several tens of pF, capacitance of the clamp capacitor Ccp and capacitance of the sampling capacitor Csp becomes extremely large and it is not realistic that the above-mentioned conditions hold. Further, when nondestructive read of signals from a pixel is possible and the signals are not summed, by reading out each sampling capacitors plural times as if the signals are summed, the above-mentioned circuit gain becomes Ccp/(Ccp+Csp) and the gain reduction does not occur. However, to read out plural times, a problem that the readout time is three times as long as usual occurs.